1. Technical Field
The present invention relates to semiconductor integrated circuits, and more particularly, to semiconductor integrated circuits with output buffer devices.
2. Related Art
A data output buffer device used in a semiconductor circuit may serve as a device that outputs internal data to an external output terminal of a chip such as a DRAM (dynamic random access memory). The data output buffer device may be designed in consideration of a high or low level output voltage level margin, output voltage-current matching, a decoupling cap, a slew rate, etc.
The slew rate represents a maximum amount of change of an output voltage with respect to a unit time. Exemplifying an output circuit which has a gain of 1, an output voltage immediately rises from 0V to 1V in an ideal circuit when an input voltage increases from 0V to 1V. However, in an actual circuit with a slew rate of K, an output voltage does not simultaneously rise in conformity with an input voltage. Instead, the output voltage rises to 1V as a ramp function with a slope of K. Therefore, it is important to control the slew rate of an output circuit to conform to the specification of a product. When there are large and small slew rates, an intensity for driving a signal, that is, a driving force, is large and small. In the case of an output buffer device including a MOS transistor, a slew rate may depend on an amount of current that can flow through the MOS transistor.
An application connected to a semiconductor memory apparatus may use a termination resistance (Rtt) and a termination voltage (Vtt) to substantially prevent signal distortion by a reflection effect occurring at a far end due to impedance mismatching in signal transmission channels as the frequency of a signal outputted from the semiconductor memory apparatus increases.
Semiconductor memory apparatuses are used in various applications such as digital TVs, printers, digital cameras, etc. Memories fabricated to be optimized for such various applications are called consumer memories. Consumer memories are not used according to the same specification, but are separately designed and fabricated in conformity with the characteristics of the respective applications. As the use of consumer memories has gradually expanded, revision costs incurred for redesigning memory apparatuses having similar functions to be suited for different applications has increased.
Among the applications using the consumer memories, applications which do not use a termination resistance (Rtt) and a termination voltage (Vtt) exist. In this case, data output characteristics are likely to be degraded.
FIG. 1 is a circuit diagram illustrating a conventional output buffer device when a termination resistance (Rtt) and a termination voltage (Vtt) are used by an external receiver of an application.
A conventional output buffer device may include a pre driver unit 100 and a main driver unit 200. The pre-driver unit 100 may be configured to receive a pre pull up signal PUP and a pre pull down signal PDN as a pre drive signal and output a pull up signal UP and a pull down signal DN as a main drive signal. The main driver unit 200 may be configured to receive the main drive signal and output output data to an output terminal.
In response to the main drive signal, the main driver unit 200 may output the output data to the output terminal by swinging the output data to the level of an output power supply voltage VDDQ or an output ground voltage VSSQ. The output data may be swung with a slew rate due to the current properties of the transistors included in the main driver unit 200.
The outputted data may be transmitted to an external receiver connected to the main driver unit 200 by way of a bus. A bus resistance Rs is a resistance of a bus that connects the output terminal and the external receiver.
The external receiver may have a termination resistance Rtt to which a termination voltage Vtt is applied. The existence of the termination resistance Rtt and the termination voltage Vtt may vary depending upon an application connected. As stated above, among applications using consumer memories, applications which do not use the termination resistance Rtt and the termination voltage Vtt exist.
If the output buffer device is turned off and resumes the state of not driving the bus, that is, a high impedance (high-Z) state, the voltage level of the bus may change to the level of the termination voltage Vtt due to the termination voltage Vtt. The termination voltage Vtt may serve as a reference voltage for an output. When the output buffer device is changed from the off state, that is, the high impedance (high-Z) state, to the on state of driving output data, a middle point of signal swing may result. The termination voltage Vtt in the specification of a DRAM has a middle level (VDDQ/2) between the output power supply voltage VDDQ and the output ground voltage VSSQ. If the output buffer device is turned on and drives output data, the voltage level of the output terminal may change from the existing termination voltage Vtt=VDDQ/2 to the output power supply voltage VDDQ or the output ground voltage VSSQ. The change range at this time may correspond to one half (VDDQ/2) of the output power supply voltage VDDQ.
In the case of an application that does not use the termination resistance Rtt and the termination voltage Vtt in the external receiver, in the high impedance (high-Z) state in which the output buffer device is turned off, the voltage level of the bus may have a random value between the output power supply voltage VDDQ and the output ground voltage VSSQ applied to the output buffer device. In the high impedance (high-Z) state, when the output buffer device is turned on and starts to drive output data, the change range of the voltage level of first output data from the output terminal may be unpredictable. In the worst case, the change range of the voltage level of first output data from the output terminal may be the level of the output power supply voltage VDDQ since the voltage level of the first output data may change from the output power supply voltage VDDQ to the output ground voltage VSSQ or vice versa. In the worst case, the change range may increase by VDDQ/2 when compared to the case of using the termination resistance Rtt and the termination voltage Vtt. Accordingly, as access time to the first data is retarded, data eye may decrease or an access time from a clock (Tac) may lengthen, whereby data output characteristics are likely to be degraded.